1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a MIS type semiconductor device, the method including an improved step of forming contact holes for source and drain regions.
2. Description of the Prior Art
Recent trends for higher integration and micropatterning of semiconductor integrated circuits, especially MOSICs, are remarkable. Along with this, gates having a size on the order of one micron or submicrons are being used in MOSICs. Micropatterning of semiconductor elements has depended upon size reduction by development of lithography techniques. However, when the element size is reduced to the order of one micron or submicrons, the elements cannot be highly integrated and operated at high speed by means of only a reduction in the sizes of gate electrodes, wiring layers, the impurity regions and contact holes. For example, a self-aligning contact technique is required to self align contact holes of impurity regions (i.e., source and drain regions) and wiring layers with gate electrodes and impurity regions.
A new contact hole formation method using a self-aligning technique was recently proposed by Muramoto et. al. in "A New Self-Aligning Contact Process for MOS LSI", IEDM, 1978, pp. 185-188. According to this method as illustrated in FIGS. 1(A) to 1(E) on p. 187 of this article, a gate oxide film is formed in an island element region surrounded by a silicon oxide field film, an arsenic-doped polycrystalline silicon layer is formed to cover the entire surface of the resultant structure, and a silicon nitride film is formed on the polycrystalline silicon layer. The silicon nitride film is selectively etched by plasma-reactive-sputter etching. The residual nitride film covers a portion of the polycrystalline silicon film which corresponds to prospective gate electrodes, contact holes, and a wiring layer. Thereafter, the polycrystalline silicon film is etched to a depth which is half the thickness thereof by using the residual silicon nitride film as a mask.
An impurity is ion-implanted through the residual thin polycrystalline silicon film by using the residual nitride silicon film as a mask, and arsenic is diffused from the residual polycrystalline silicon film into the substrate to form source and drain regions.
Thereafter, a silicon nitride film portion is left in the contact hole regions, and another portion of the silicon nitride film is etched, and the polycrystalline silicon film is selectively oxidized. By this selective oxidation of the polycrystalline silicon film, only a polycrystalline silicon film portion which excludes a portion corresponding to the contact hole regions and the gate electrode region is oxidized. The resultant oxidized polycrystalline silicon portion constitutes an intermediate insulating layer. The nonoxidized polycrystalline silicon portion constitutes a first wiring layer which directly contacts the source and drain regions.
According to this method by S. Muramoto et. al., the number of mask alignment operations can be decreased. In addition, a second wiring layer to be formed on the field oxide film can electrically contact the source and drain regions through the first wiring layer of polycrystalline silicon. As compared with the case wherein contact holes are formed by conventional photolithography techniques, mask alignment with the field oxide film requires only coarse alignment to form the contact holes.
However, in order to obtain a complete insulating effect of the oxidized polycrystalline silicon film according to the above method, polycrystalline silicon must be selectively oxidized at a high temperature (e.g., 850.degree. C. or more) an undisclosed period of time. As a result, an oxidized polycrystalline silicon film portion is formed under the silicon nitride film acting as an oxidation mask, and the shape of the gate electrode changes. In addition to this disadvantage, the high temperature for selective oxidation of polycrystalline silicon causes the impurity regions already formed in the substrate to excessively extend in the substrate. Therefore, junction and gate capacitances increase and, as a result, prevent high-speed operation of the element.